1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to an apparatus of driving a plasma display panel capable of accurately detecting a temperature of the plasma display panel for a stable driving of the plasma display panel.
2. Description of the Related Art
Recently, various flat panel devices have been developed that reduce weight and bulk, which are drawbacks of the cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP), an electro-luminescence display (ELD) device, and the like.
The PDP of these flat panel display devices displays pictures by using a plasma discharge. The PDP has been used for high-resolution televisions, monitors and internal or external advertising display devices because it has a rapid response speed and is suitable for displaying a large-area picture.
Referring to FIGS. 1 and 2, a related art PDP includes a panel 10, a printed circuit board (PCB) 18 for driving the panel 10 and a heat-proof plate 20 attached to a rear surface of the panel 10.
The panel 10 includes: an upper substrate 10a having a plurality of scan electrodes and a plurality of sustain electrodes; and a lower substrate 10b having a plurality of address electrodes formed in a direction crossing the scan electrodes and the sustain electrodes, and a phosphorous material layer formed on an entire surface of the substrate. A phosphorous material generates a visible ray by a discharge between the scan electrodes and the sustain electrodes, and the address electrodes, and adjusts a transmittance of the visible ray to display a designated picture.
The heat-proof plate 20 supports the panel 10 and serves to radiate a heat generated upon driving of the panel 10. The heat-proof plate 20 is made of a metal material with a good thermal conductivity, for example, aluminum (Al), for making a radiation well.
The panel 10 requires a plurality of driver integrated circuits (ICs), connected to the scan electrodes and the address electrodes, for supplying a data signal and a scanning signal. The driver ICs include a scan driver IC 3 and a data driver IC2. Each of the driver ICs is installed between the PCB 18 and the panel 10, and supplies a driving signal to the panel 10 in response to a control signal supplied from the PCB 18. To this end, the PCB 18 and the panel 10 are connected to each other by mean of a flexible printed circuit (FPC) 14. If the driver ICs are packaged by way of a chip on film (COF) system, one side of the FPC 14 is connected to an IC chip 16 of the scan and the data drivers 3 and 2, and other side of the FPC 14 is connected to pads 12 connected to driving electrodes of the panel 10.
A case 30 is installed to protect the PDP from an external impact when the PDP is produced.
Such a PDP is driven by a time-divisional scheme in which one frame is divided into various sub-fields having a different emission frequency, so as to realize gray levels of a picture. Each sub-field is again divided into an initialization period for initializing the entire field, an address period for selecting a scan line and selecting the cell from the selected scan line and a sustain period for expressing gray levels depending on the discharge frequency.
Herein, the initialization period is again divided into a set-up interval during which a rising ramp waveform is supplied and a set-down interval during which a falling ramp waveform is supplied. For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields SF1 to SF8 as shown in FIG. 2. Each of the 8 sub-field SF1 to SF8 is divided into the initialization period, the address period and the sustain period as mentioned above. Herein, the initialization period and the address period of each sub-field are equal for each sub-field, whereas the sustain period and the number of sustain pulses assigned thereto are increased at a ratio of 2n (where n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field.
FIG. 4 shows a driving waveform of the PDP applied to two sub-fields.
In FIG. 4, Y represents the scan electrode, Z represents the sustain electrode, and X represents the address electrode.
Referring to FIG. 4, the PDP is divided into an initialization period for initializing the full field, an address period for selecting a cell, and a sustain period for sustaining a discharge of the selected cell for its driving.
In the initialization period, a rising ramp waveform Ramp-up is simultaneously applied to all of the scan electrodes Y in a set-up interval. This rising ramp waveform Ramp-up causes a weak discharge within cells of the full field to generate wall charges within the cells. In the set-down interval, after the rising ramp waveform Ramp-up was supplied, a falling ramp waveform Ramp-down falling from a positive voltage lower than a peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes Y. The falling ramp waveform Ramp-down causes a weak erasure discharge within the cells, to thereby erase spurious charges of wall charges and space charges generated by the set-up discharge and uniformly leave wall charges required for the address discharge within the cells of the full field.
In the address period, a negative scanning pulse Scan is sequentially applied to the scan electrodes Y, and, at the same time, a positive data pulse Data is applied to the address electrodes X. A voltage difference between the scanning pulse Scan and the data pulse Data is added to a wall voltage generated in the initialization period to thereby generate an address discharge within the cells to which the data pulse Data is supplied. Wall charges are formed within the cells selected by the address discharge.
Meanwhile, a positive direct current voltage having a sustain voltage level Vs is applied to the sustain electrodes Z during the set-down interval and the address period.
In the sustain period, a sustaining pulse Sus is alternately applied to the scan electrodes Y and the sustain electrodes Z. Then, a wall voltage within the cell selected by the address discharge is added to the sustain pulse Sus to thereby generate a sustain discharge taking a surface-discharge type between the scan electrode Y and the common sustain electrode Z whenever each sustain pulse Sus is applied. Finally, after the sustain discharge has been finished, an erasing ramp waveform Erase having a small pulse width is applied to the sustain electrode Z to thereby erase wall charges left within the cells.
However, if the related art PDP is operated at a low temperature, then a brightness point erroneous fire occurs. In other words, as the result of an operation characteristic at a low-temperature, the PDP in accordance with the operation temperature causes the brightness point erroneous fire at a plurality of discharge cells. It has been supposed that such a brightness point erroneous fire occurs because a motion of particles becomes dull at the low temperature.
More specifically, if a motion of particles becomes dull at a low temperature, then an erasure discharge caused by the erasing ramp waveform Erase may be not normally generated. Wall charges formed in the scan electrode Y and the sustain electrode Z are not erased from cells in which such an erasure discharge has not been normally generated.
Thereafter, in the set-up interval, a positive rising ramp waveform Ramp-up is applied to the scan electrode Y. At this time, since negative wall charges has been formed at the scan electrode Y, that is, since the polarity of a voltage applied to the scan electrode Y is contrary to that of wall charges formed in the scan electrode Y, a normal discharge is not generated in the set-up interval. Thus, a normal discharge is not generated in the set-down interval following the set-up interval. As described above, if the normal discharge does not occur in the initialization period, then wall charges excessively formed in the erasure period make an affect to the address period and the sustain period. In other words, a strong discharge entailing an undesired shape of brightness point is generated in the sustain period due to the wall charges formed excessively in the discharge cells. Thus, in order to prevent the brightness point erroneous fire at the low temperature, the PDP detects a peripheral temperature by a temperature sensor 17 installed in the PCB 18 as shown in FIG. 2 to apply a driving waveform for a driver to suit with a temperature of the driver, to thereby make to display.
However, since a voltage property and a waveform property of a module according to the peripheral surrounding are different, all of the driving properties of a panel can be adjusted in accordance with a temperature, but a reference surrounding temperature and an actual temperature of the panel have a lot of difference. That is, since the temperature sensor 17 is built in the PCB 18 and detects the temperature of the panel 10, it is impossible to detect an accurate temperature and it is difficult to compensate an error caused by the temperature.